The present invention relates to a lateral, double-diffused transistor (e.g. an LDMOS) having improved breakdown characteristics, particularly suited for high voltage integrated circuits (HVICs).
Typically, high-voltage, integrated circuits (HVICs) contain one or more high-voltage power transistors together with a low voltage signal processing circuitry on the same chip. The use of this type of integrated circuits is becoming more and more widespread as a viable alternative to the use of a plurality of discrete circuits, in a wide variety of applications.
In these integrated circuits, lateral, double-diffused, MOS transistors (LDMOS) are widely used as active power devices.
One way to improve the voltage handling capability of a lateral transistor is a so-called RESURF technique. ("RESURF" is an acronym for REduced SURface Field.) This particular technique is described in an article of J. A. Appels et al. at 35 PHILIPS J. RES. 1-13 (1980), the content of which is herein incorporated by express reference. The physical structure of a RESURF LDMOS transistor, as depicted in FIGS. 1 and 2, is substantially identical to the structure of a conventional LDMOS transistor. The main difference between the two devices consists in the fact that the structure of a RESURF LDMOS is generally formed in a much thinner epitaxial layer than a conventional high voltage device. For this reason, the bottom-side depletion region pertaining to the junction between the epitaxial layer, for example of an n- conductivity, and a substrate layer, for example of a p- conductivity, has a significant effect on high-voltage withstanding capability in the case of a RESURF type LDMOS structure.
For better illustrating the breakdown mechanism in a RESURF LDMOS structure, FIGS. 3, 4 and 5 show in a qualitative and schematic way the progress of the depletion region into the drift region (the region where electric charge carriers move under the influence of an electric field).
The situations that develop in the drift region with an increase of the voltage applied to a drain terminal (D), in a grounded-source configured transistor, are schematically depicted in FIGS. 3, 4 and 5, wherein the depleted region is identified with crosshatching. The operating condition characterized by a relatively low voltage applied to the drain terminal of the device, i.e. a voltage lower than the "pinch-off" voltage (V.sub.d &lt;V.sub.PO), is depicted in FIG. 3. As may be observed, in such a low drain voltage condition, practically no interaction exists between the surface depletion region that develops under a gate structure (G) and the bottom-side depletion region (or more briefly bottom depletion region) that develops across the junction between the substrate and the epitaxial layer. In these conditions, the electric fields pertaining to the superficial regions of the structure will have values similar to those that occur in a conventional type LDMOS structure (i.e. in a similar transistor structure formed in a relatively thicker epitaxial layer).
Upon an increase of the voltage applied to the drain (D) of the transistor, and when such a voltage reaches a "pinch-off" value (VD=VPO), the two depleted regions (surface and bottom regions) merge. This "pinch-off" condition is schematically depicted in FIG. 4. Because of an expansion of the depletion region in the drift region, the increase of the electric field intensity under the edge of the gate electrode tends to be less than in the case of a conventional LDMOS structure.
When the voltage applied to the drain (D) of the device rises above the pinch-off voltage (VD&lt;VPO), the surface depletion region tends to extend laterally toward the drain region (the n+ region in the case shown in the Figures), and eventually the whole drift region becomes completely depleted. This may occur as long as the electric field that develops under the edge of the gate electrode during such a lateral extension of the surface depletion region remains lower than the critical electric field (at which avalanche breakdown may occur). Under these conditions, as schematically shown in FIG. 5, the drift region under the edge of the gate electrode becomes practically isolated from the drain region and therefore the local electric field intensity remains approximately constant even if the drain voltage is increased further.
Thus, under these conditions in a grounded source configuration, the breakdown mechanism of the device is determined solely by the presence of intense electric fields near the drain diffusion (n+) or at the junction between the substrate and the epitaxial layer. However, in general the main objectives in designing a power transistor are:
1) reducing its internal resistance (ON-resistance) and PA0 2) achieving the highest possible breakdown voltage.
These two objectives could be reached if the drift region was completely depleted just before electric fields of critical intensity would develop under the edge of the gate electrode. This would ensure that the device be in a working condition as the one depicted in FIG. 5; a condition that determines the best avalanche breakdown voltage that can be obtained for a certain charge density in the drift region. In other words, an optimal RESURF structure should operate under conditions of substantially complete depletion when the voltage that is applied to a drain terminal reaches or slightly rises above the pinch-off voltage (VD=VPO).
According to the known art, these objectives may be achieved or approached by accurately trimming common design parameters, such as for example the doping level of the epitaxial layer, the doping level of the substrate layer, the thickness of the field oxide and in particular the thickness and resistivity of the epitaxial layer. Optimization of the structure thus becomes a very critical process because while from one side a complete depletion region of the drift region must be favored, on the other side, the structure should retain the ability to withstand voltage breakdown between, for example, the source region p+ and the substrate p-, under punch-through conditions.
In contrast to the limitations of this state of the art, the disclosed innovations provide a way to optimize an integrated structure of a RESURF transistor in a noncritical way. This is accomplished by providing an additional degree of freedom in designing the structure, and thereby permitting achievement of a complete depletion of the drift region, irrespective of breakdown withstanding considerations pertaining to a punch-through mechanism between a source region and the substrate of the integrated structure. (Source-substrate breakdown conditions are particularly likely to occur when the transistor is functioning in a source follower configuration.)
Depletion width at a junction, for a given applied voltage, is related to the volume integral (over the volume within the depletion boundaries) of ionized dopant atoms; and therefore, by increasing the net concentration of dopant atoms below the metallurgical boundary, the lower depletion width is decreased and the upper depletion width is increased.
According to disclosed innovative embodiments, this is obtained by forming a buried region having a doping level higher than the doping level of the substrate, between the substrate and the epitaxial layer and projectively underneath the drain region. This buried region is kept at a sufficiently large distance from a source region so that a punch-through between the source region and the buried region (because of the curvature effect that the buried region may induce, though in an extremely limited fashion) does not become a limiting parameter in the functioning of the device at the design voltages.
This buried region may be formed by ion implanting the substrate, within a defined area, before going through the normal steps of a standard fabrication process of these devices that bring about the formation of buried layers in general and the growth of the epitaxial layer.
This buried region extends for a major part of its "thickness" into the substrate. Preferably there is no ohmic contact path between the buried region and any other regions or conducting layers.
In practice, this buried region permits the device designer to "modulate" the depletion along the junction between the epitaxial layer and the substrate in an important zone (underlying the drain region of the device) differently from other zones, and in particular from the zone underlying the source region of the structure. In this way, a complete depletion of the drift region at the drain end, from the horizontal junction up to the surface, is favored without necessarily modifying the values of other physical parameters of the integrated structure, such as for example without further decreasing the thickness of the epitaxial layer, or increasing the doping level of the epitaxial layer, both of which would be detrimental in terms of punchthrough.
According to a disclosed class of innovative embodiments, there is provided: A transistor, for operation at a known maximum operating source/drain voltage, comprising: a substrate which includes at least one substantially monolithic body of semiconductor material of a first conductivity type; a semiconductor epitaxial layer of a second conductivity type atop said substantially monolithic body; a lateral transistor, at a surface of said epitaxial layer, comprising source, gate, and drain regions with said gate region being laterally interposed between said source and drain regions to control current flow therebetween; and a first portion of a patterned buried layer, at the boundary between said substrate and said epitaxial layer, in locations such that said drain, but NOT said source, lies thereabove; wherein said epitaxial layer has a thickness and doping such as to be fully depleted, in locations between said source and drain, when said predetermined maximum operating source/drain voltage is applied to said source and drain.
According to another disclosed class of innovative embodiments, there is provided: A transistor, comprising: a substrate which includes at least one substantially monolithic body of semiconductor material of a first conductivity type; a semiconductor epitaxial layer of a second conductivity type atop said substantially monolithic body; a lateral transistor, at a surface of said epitaxial layer, comprising source, gate, and drain regions with said gate region being laterally interposed between said source and drain regions to control current flow therebetween; and a first portion of a patterned buried layer, at the boundary between said substrate and said epitaxial layer, in locations such that said drain, but NOT said source, lies thereabove; wherein no ohmic connection to said buried layer exists except through said substrate.
According to another disclosed class of innovative embodiments, there is provided: A transistor, for operation at a known maximum operating source/drain voltage, comprising: a substrate which includes at least one substantially monolithic body of semiconductor material of a first conductivity type; a semiconductor epitaxial layer of a second conductivity type atop said substantially monolithic body; a lateral transistor, at a surface of said epitaxial layer, comprising source, gate, and drain regions with said gate region being laterally interposed between said source and drain regions to control current flow therebetween; and a first portion of a patterned buried layer, at the boundary between said substrate and said epitaxial layer, in locations such that said drain, but NOT said source, lies thereabove; wherein said epitaxial layer has a thickness and doping such as to be fully depleted, in locations between said source and drain, when said predetermined maximum operating source/drain voltage is applied to said source and drain; and wherein said buried layer laterally surrounds said drain on all sides thereof.
According to another disclosed class of innovative embodiments, there is provided: A transistor, comprising: a substrate which includes at least one substantially monolithic body of semiconductor material of a first conductivity type; a semiconductor epitaxial layer of a second conductivity type atop said substantially monolithic body; a lateral transistor, at a surface of said epitaxial layer, comprising source, gate, and drain regions with said gate region being laterally interposed between said source and drain regions to control current flow therebetween; and a first portion of a patterned buried layer, at the boundary between said substrate and said epitaxial layer, in locations such that said drain, but NOT said source, lies thereabove; wherein said source and drain regions define a first lateral separation therebetween, and said source region and said buried layer define a second lateral separation therebetween which is more than 30% and less than 100% of said first lateral separation.
According to another disclosed class of innovative embodiments, there is provided: A transistor, for operation at a known maximum operating source/drain voltage, comprising: a substrate which includes at least one substantially monolithic body of semiconductor material of a first conductivity type; a semiconductor epitaxial layer of a second conductivity type atop said substantially monolithic body; a lateral transistor, at a surface of said epitaxial layer, comprising source, gate, and drain regions with said gate region being laterally interposed between said source and drain regions to control current flow therebetween; and a first portion of a patterned buried layer, at the boundary between said substrate and said epitaxial layer, in locations such that said drain, but NOT said source, lies thereabove; wherein said epitaxial layer has a thickness and doping such as to be fully depleted, in locations between said source and drain, when said predetermined maximum operating source/drain voltage is applied to said source and drain.
According to another disclosed class of innovative embodiments, there is provided: An integrated circuit, comprising: a substrate which includes at least one substantially monolithic body of semiconductor material of a first conductivity type; a semiconductor epitaxial layer of a second conductivity type atop said substantially monolithic body; a lateral high-voltage transistor, at a surface of said epitaxial layer, comprising source, gate, and drain regions with said gate region being laterally interposed between said source and drain regions to control current flow therebetween; a first portion of a patterned buried layer, at the boundary between said substrate and said epitaxial layer, in locations such that said drain, but NOT said source, lies thereabove; and a plurality of low-voltage transistors integrated in said epitaxial layer; wherein at least some ones of said low-voltage transistors overlie other portions of said patterned buried layer.
According to another disclosed class of innovative embodiments, there is provided: An integrated circuit, comprising: a substrate which includes at least one substantially monolithic body of semiconductor material of a first conductivity type; a semiconductor epitaxial layer of a second conductivity type atop said substantially monolithic body; a lateral high-voltage transistor, at a surface of said epitaxial layer, comprising source, gate, and drain regions with said gate region being laterally interposed between said source and drain regions to control current flow therebetween; a first portion of a patterned buried layer, at the boundary between said substrate and said epitaxial layer, in locations such that said drain, but NOT said source, lies thereabove; and a plurality of low-voltage transistors formed in said epitaxial layer; wherein said low-voltage transistors include at least some P-channel field-effect transistors which are formed over additional portions of said patterned buried layer, and wherein said low-voltage transistors include at least some PNP transistors which are formed over further portions of said patterned buried layer.
According to another disclosed class of innovative embodiments, there is provided: A lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a semiconducting substrate having a second type of conductivity, comprising: a drain region in said epitaxial layer; a buried region having the same type of conductivity of said substrate and a doping level higher than said semiconducting substrate, between said substrate and said epitaxial layer in a zone lying beneath said drain region of the transistor.
According to another disclosed class of innovative embodiments, there is provided: A fabrication method, comprising the steps of: (a.) providing a substrate which includes at least one substantially monolithic body of semiconductor material of a first conductivity type; (b.) performing a patterned implantation step, to introduce additional dopants of said first conductivity type into said substrate; (c.) growing an epitaxial semiconductor layer of a second conductivity type atop said substrate; (d.) forming source, gate, and drain regions at a surface of said epitaxial layer, with said gate region being laterally interposed between said source and drain regions to control current flow therebetween, in locations such that said drain, but NOT said source, lies above said additional dopants introduced in said step (b).
According to another disclosed class of innovative embodiments, there is provided: A method for improving the breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a semiconducting substrate of a second type of conductivity and comprising a drain region formed in said epitaxial layer which is contacted through a drain contact, characterized by forming a buried region having the same type of conductivity of the substrate and a doping level higher than the doping level of the substrate, between the substrate and said epitaxial layer in a zone beneath the drain region of the transistor.
According to another disclosed class of innovative embodiments, there is provided: A method for favoring depletion of a drift region comprised between a source region and a drain region of a lateral transistor, integrated in an epitaxial layer of a first type of conductivity grown on a semiconducting substrate of a second type of conductivity, comprising forming a buried region having the same type of conductivity of said substrate and a doping level higher than the doping level of the substrate, between the substrate and said epitaxial layer, in a zone beneath said drain region of the transistor.
According to some embodiments, the source and drain regions define a first lateral separation therebetween, and the source region and the buried layer define a second lateral separation therebetween which is more than 30% but less than 100% of the first lateral separation.
According to some embodiments, the regions define a first lateral separation therebetween, and the source region and the buried layer define a second lateral separation therebetween which is more than % of the first lateral separation.
According to some embodiments, the epitaxial layer has a thickness and doping such as to be fully depleted, in locations between the source and drain, when a known maximum operating source/drain voltage difference is applied to the source and drain.
According to some embodiments, the drain overlies the buried layer and the lateral boundaries of the drain lie completely within the lateral boundaries of said buried layer.
According to some embodiments, additional buried layer portions which are separate from the first buried layer portion are also provided.